1. Field of the Invention
The present invention relates generally to electrical circuits and, more particularly, to systems and methods for clock and data recovery.
2. Related Art
In a typical serial link non-return-to-zero (NRZ) modulated receiver (e.g., a Universal Serial Bus (USB) 3.0 device, an optical transceiver, or other device), clock information is embedded in an incoming data signal to lower chip pin count and power. Clock and data recovery (CDR) is traditionally used inside the receiver to recover a clock signal from the incoming data signal. Data can then be recovered from the incoming data signal using the recovered clock in a relatively straightforward manner.
Conventionally, a phase-locked loop (PLL) circuit may be used to perform CDR operations including frequency acquisition and phase locking. As is well known, the oscillation frequency of an on-chip voltage controlled oscillator (VCO) of a PLL circuit may exhibit a large process-voltage-temperature (PVT) spread. Accordingly, a first task of a PLL circuit is typically to perform a frequency/phase detection to pull the VCO oscillation frequency clock close to the recovery clock frequency. The pull-in range (e.g., the largest frequency deviation that can be reliably locked) of the frequency/phase detection may be relatively small if the incoming data signal is used as a reference. To solve this problem, a reference clock with a small frequency deviation (e.g., less than approximately one percent) may be used as the reference. The frequency of the reference clock may have a constant relationship to the data baud frequency of the incoming data signal (e.g., which corresponds to the far-end modulation clock frequency). For example, the data baud frequency may be an integer or fractional multiple (e.g., greater than one) of the reference clock frequency.
After frequency acquisition is performed, the PLL circuit is typically switched from using the reference clock to using the incoming data signal as a reference. The PLL circuit then performs a phase locking operation to lock the VCO oscillation frequency with the frequency of the incoming data.
A conventional loop filter of a PLL circuit typically includes either a charge pump (e.g., including one or more passive filters) or an active filter (e.g., including one or more input resistors). If the data baud frequency of the incoming data signal is very high (e.g., a Super Speed USB 3.0 signal operating at approximately 5 Gbps), the output signal of the phase detector (e.g., a linear phase detector providing a predictable loop bandwidth and damping factor for the PLL circuit) may be much higher than 5 GHz depending on the clock phase of the VCO and the data phase of the incoming data signal. However, in a conventional PLL circuit where a charge pump is utilized as a loop filter, the high frequency output signal of the phase detector may have difficulty switching the input differential pair of the charge pump while still maintaining reasonable power consumption. Thus, in conventional PLL circuits, the high frequency output signal of the phase detector may be effectively blocked by the charge pump.
Also in a conventional PLL circuit using an active filter including one or more input resistors, if the VCO oscillation frequency (e.g., approximately 5 GHz) is much higher than the reference clock frequency (e.g., approximately 20 MHz), then the output frequency of the phase-frequency detector may be much lower than 5 GHz. However, in this case, the open loop gain of the active filter may be 250 times lower when performing frequency/phase detection operations than when performing phase locking operations. As a result, the conventional PLL circuit may exhibit a large static phase offset when performing frequency/phase detection operations.
As a result, there is a need for an improved approach to the detection and recovery of clocks associated with incoming data signals.